1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a technique for designing a semiconductor memory device of a small capacity (e.g., 4 Mbit) by slightly changing a design of a semiconductor memory device of a large capacity (e.g., 8 Mbit).
2. Description of Related Art
Users individually have various demands for a capacity of a semiconductor memory device such as a flash memory. In response to the users' demands, manufacturers of semiconductor memories are required to offer a lineup of semiconductor memories of various capacities as products.
However, it is not preferable from the viewpoint of a manufacturing cost to individually offer the lineup of the semiconductor memory device products of the various capacities as individual products. Individual designs and manufacturing processes of the semiconductor memory device products of the various capacities increase time and effort in designing and manufacturing the semiconductor memory device products, so as to raise the production cost.
One of approaches to solve the above-described problems is to fix a part of address bits (typically, a higher-order address bit) in a semiconductor memory device of a large capacity by changing the design of a wiring layer, thereby providing a semiconductor memory device of a pseudo-small capacity. For example, if the highest-order address of a semiconductor memory device of a capacity of 8 Mbit is fixed inside, the semiconductor memory device functions as a semiconductor memory device of a capacity of 4 Mbit. In the same manner, if two higher-order address bits are fixed inside, the semiconductor memory device functions as a semiconductor memory device of a capacity of 2 Mbit. The above-described technique is often called “cutting-down”. Manufacturing of a semiconductor memory device of a small capacity by the cutting-down is effective in reducing the production cost since most of designing and manufacturing processes can be commonly used for both of the semiconductor memory device of the large capacity and the semiconductor memory device of the small capacity.
The cutting-down is particularly effective in a case where miniaturization of processes sufficiently proceeds with respect to a size of a semiconductor memory device. As the miniaturization of the processes proceeds, a ratio of the size of a peripheral circuit (other than a memory array) to the chip size of the entire semiconductor memory device relatively becomes higher. In the case of the higher ratio of the size of the peripheral circuit, a difference between a chip size of a product of a small capacity and a chip size of a product of a large capacity is small. In this case, the common processes for designing and manufacturing the semiconductor memory device bring about more significant advantages than an increase in chip size per capacity by the cutting-down.
However, I have now discovered that the manufacturing of the semiconductor memory device of the small capacity by the cutting-down raises an unnecessary decrease in yield. For example, assume that the semiconductor memory device of the capacity of 8 Mbit is made to function as the semiconductor memory device of the capacity of 4 Mbit. Even if a deficiency, which cannot be remedied, is found in an inspection process of the memory cell of 4 Mbit which is one part of the semiconductor memory device of 8 Mbit and will be actually used, no deficiency may be found in the memory cell of 4 Mbit which is another part of the semiconductor memory device of 8 Mbit and won't be actually used. However, when the technique for fixing the higher-order address bit by changing the design of the wiring layer is used, the memory cell of 4 Mbit which possibly has no deficiency cannot be used.
Japanese Laid-Open Patent Application JP-A2004-265162 (corresponding to U.S. Pat. No. 7,197,595B2) discloses a technique for avoiding a block including a deficient bit, selecting a block to be used, and assigning an address to the selected block. However, the technique disclosed in JP-A2004-265162 cannot cope with a semiconductor memory device which functions as a semiconductor memory device having a pseudo-small capacity by fixing a part of address bits according to a design change.